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DSP Core Programming Model
6.6.4 Host Data Register (HDR)
The HDR register holds the data value of the corresponding bits of the HI08 signals configured as
GPIO signals. The functionality of D xx depends on the corresponding HDDR bit (that is,
DR xx ).The host processor can not access the Host Data Register (HDR)
15
D15
14
D14
13
D13
12
D12
11
D11
10
D10
9
D9
8
D8
7
D7
6
D6
5
D5
4
D4
3
D3
2
D2
1
D1
0
D0
Figure 6-9. Host Data Register (HDR) (X:$FFFFC8)
Table 6-10. HDR and HDDR Functionality
HDDR
HDR
DRxx
GPIO Signal 1
Dxx
Non-GPIO Signal 1
0
1
Read-only bit—The value read is the binary value of
the signal. The corresponding signal is configured as
an input.
Read/write bit— The value written is the value read.
Read-only bit—Does not contain significant data.
Read/write bit— The value written is the value read.
The corresponding signal is configured as an output
and is driven with the data written to Dxx.
1. Defined by the selected configuration.
6.6.5 Host Base Address Register (HBAR)
In multiplexed bus modes, HBAR selects the base address where the host-side registers are
mapped into the host bus address space. The address from the host bus is compared with the base
address as programmed in the Base Address Register. An internal chip select is generated if a
match is found. Figure 6-11 shows how the chip-select logic uses HBAR.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BA10 BA9
BA8
BA7
BA6
BA5
BA4
BA3
—Reserved bit, read as 0, write to 0 for future compatibility.
Figure 6-10. Host Base Address Register (HBAR) (X:$FFFFC5)
Table 6-11. Host Base Address Register (HBAR) Bit Definitions
Bit Number
15–8
7–0
Bit Name
BA[10–3]
Reset Value
0
$80
Description
Reserved. Write to 0 for future compatibility.
Base Address
Reflect the base address where the host-side registers are mapped into
the bus address space.
DSP56311 User’s Manual, Rev. 2
Freescale Semiconductor
6-15
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